The present invention relates to a frame synchronizing circuit which establishes frame synchronization by detecting a predetermined sync (synchronization) pattern in a frame or frames.
Conventionally, in transmitting digital data by frame, a technique is commonly employed that a sync pattern is incorporated in each frame at a predetermined position and frame synchronization is established on the reception side by detecting it. For example, Japanese Patent Laid-Open Publications Nos. 5-37515, 63-236434, and 6-164572 have disclosed various frame synchronizing circuits in which a main synchronization circuit and an auxiliary synchronization circuit are combined.
As disclosed in the above publications, by virtue of the presence of the auxiliary synchronization circuit in addition to the main synchronization circuit, even if the main synchronization circuit is rendered in a pseudo-synchronization state, another synchronization state can be established.
In the frame synchronizing circuit disclosed in Japanese Patent Laid-Open Publication No. 5-37515, a judgment circuit compares the number of errors detected by the main synchronization circuit with the number of errors detected by the auxiliary synchronization circuit to judge whether the main synchronization circuit is in a pseudo-synchronization state; if the former number is larger than the latter number, the sync position of the auxiliary synchronization circuit is set as a sync position of the main synchronization circuit. Because of execution of a large number of steps, the frame synchronizing circuit has a problem that it takes long time to establish synchronization again.
In the frame synchronizing circuit disclosed in Japanese Patent Laid-Open Publication No. 63-236434, an unprotected sync position is established because the main synchronization circuit enables only forward protection. Therefore, after a synchronization state established by the main synchronization circuit is broken, in many cases a correct sync position is detected by the auxiliary synchronization circuit having a backward protection function. This frame synchronization circuit still has a problem that it takes long time until synchronization is established reliably.
In the frame synchronizing circuits disclosed in the above two publications, if a false pattern similar to the sync pattern, that is, a pseudo-sync pattern is included in frames periodically, a sync position is set based on the pseudo-sync patterns and thereafter returning to a correct sync position is disabled. As a countermeasure against such a problem, the frame synchronizing circuit disclosed in Japanese Patent Laid-Open Publication No. 6-164572 performs error detection using a CRC code. However, the auxiliary synchronization circuit in the frame synchronizing circuit starts a pull-in, synchronization operation for the next sync position when the main synchronization circuit pulls out of synchronism, is out of synchronization. Therefore, the frame synchronizing circuit has a problem that it takes long time to re-establish synchronization after it is in the out-of-sync state.